Concurrent Error Detection in Systolic Array AB^2 Multiplier Using Linear Codes
Computational Aspects of Social Networks（2010）
摘要
This investigation is based on a traditional AB^2 systolic array multiplier [16] to derive a new CED AB2 multiplier using linear block codes. A novel linear encoding algebra is derived to realize parity-check functionality. It is based on the syndrome value, and is adopted to detect errors in the multiplication. Altera FPGA with stratix families to simulate our proposed CED multiplier. In the field GF (2^72), the space overhead of the proposed circuit is around 9.1%. The latency overhead only requires extra two clock cycles. The proposed CED architecture can therefore be utilized effectively in fault-tolerant cryptosystems.
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关键词
linear codes,proposed ced multiplier,space overhead,systolic array ab,linear block code,systolic array multiplier,proposed circuit,ab2 multiplier,proposed ced architecture,novel linear encoding algebra,concurrent error detection,new ced,latency overhead,fpga,block codes,finite field,galois fields,cryptography,fault tolerant,linear algebra,encoding,field programmable gate arrays,linear code,linear block codes,polynomials,systolic array
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