A 3-D Cache With Ultra-Wide Data Bus for 3-D Processor-Memory Integration
IEEE Transactions on Very Large Scale Integration (VLSI) Systems(2010)
Abstract
Slow cache memory systems and low memory bandwidth present a major bottleneck in performance of modern microprocessors. 3-D integration of processor and memory subsystems provides a means to realize a wide data bus that could provide a high bandwidth and low latency on-chip cache. This paper presents a three-tier, 3-D 192-kB cache for a 3-D processor-memory stack. The chip is designed and fabricated in a 0.18 µm fully depleted SOI CMOS process. An ultra wide data bus for connecting the 3-D cache with the microprocessor is implemented using dense vertical vias between the stacked wafers. The fabricated cache operates at 500 MHz and achieves up to 96 GB/s aggregate bandwidth at the output.
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Key words
CMOS integrated circuits,cache storage,microprocessor chips,silicon-on-insulator,3D cache,3D processor-memory integration,CMOS process,frequency 500 MHz,memory size 192 KByte,silicon-on-insulator,size 0.18 mum,ultrawide data bus,3-D integration,FD-SOI,SRAM,cache architecture,data bus
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