A fully integrated CMOS voltage regulator for supply-noise-insensitive charge pump PLL design

In this paper, a new design of on-chip CMOS voltage regulator, which provides two stable power supplies to charge pump and voltage controlled oscillator (VCO) in charge pump phase-locked loop (PLL), is presented. A power supply noise rejection (PSNR) whose peaking is less than -40dB is achieved over the entire frequency spectrum for VCO supply. The voltage regulator provides maximum 14mA current, and static current is about 780@mA at 3.3V. Based on the proposed voltage regulator, a PLL clock generator has been developed and measured in the AMS 0.35@mm CMOS process. Operating at 160MHz, a period jitter of 13.64ps was measured under a clean power supply, while period jitter became 16.24ps under a power supply modulated with a 400mV, 10kHz square wave.