Double-Data-Rate, Wave-Pipelined Interconnect for Asynchronous NoCs
IEEE Micro（2009）
Abstract
DWP, a new interconnect structure for asynchronous networks on chip in multiprocessing SoCs, yields higher throughput, consumes less power, suffers less from crosstalk noise, and requires less area than traditional interconnect structures. Its advantages stem from techniques including wave pipelining, double-data-rate transmission, interleaved lines, misaligned repeaters, and clock gating.
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Key words
asynchronous network,crosstalk noise,wave-pipelined interconnect,interleaved line,yields higher throughput,asynchronous nocs,wave pipelining,clock gating,multiprocessing socs,misaligned repeater,double-data-rate transmission,double data rate,multiprocessor,synchronization,system on chip,interconnect,network on chip,asynchronous
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