Scalable high-throughput variable block size motion estimation architecture

Microprocessors and Microsystems(2009)

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摘要
Variable block size (VBS) motion compensated prediction (MCP) provides substantial rate-distortion performance gain over conventional fixed-block-size MCP and is a key feature of the H.264/AVC video coding standard. VBS-MCP requires the encoder to perform VBS motion estimation (VBSME), a computationally complex operation. In this paper, we propose a high motion vector throughput full-search VBSME architecture. High performance is achieved by performing parallel computations for multiple pixels within a macroblock, as well as computing several candidate motion vector (MV) positions in parallel. Two implementations of the architecture are examined, a four pixel-parallel implementation, and a higher performance 16 pixel-parallel implementation. A high degree of scalability is achieved by allowing for a variable length processing element array, where more processing elements yields a higher degree of candidate MV parallelism. The proposed architecture achieves a throughput exceeding current full-search VBSME architectures.
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关键词
high motion vector,high degree,full search,higher performance,motion compensation,parallel computation,vbs motion estimation,pixel-parallel implementation,h.264,variable block size,candidate motion vector,size motion estimation architecture,vbsme architecture,high performance,substantial rate-distortion performance gain,video coding circuit architecture,motion estimation,proposed architecture,scalable high-throughput variable block,parallel computer,high throughput
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