Analyzing the Impact of Fault-tolerant BIST for VLSI Design

Saurabh Jain,W. Robert Daasch,David Armbrust

Boston, MA（2008）

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Abstract

This paper examines fault-tolerant DfT (Design for Test) circuits as an effective approach for improved reliability and lower defective parts per million (DPPM). The paper provides a comprehensive examination of one alternative, quadded gate, inter-leaved node logic design.

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Key words

logic gates,error correction,vlsi design,fault tolerance,fault tolerant,logic design,integrated circuit,fault detection,part per million,vlsi,chip,design for testability,design for test

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