Clock Gating for Power Optimization in ASIC Design Cycle Theory & Practice

Sukumar Jairam,Madhusudan Rao,Jithendra Srinivas,Parimala Vishwanath,H. Udayakumar,Jagdish C. Rao

ISLPED（2008）

引用 27|浏览2

关键词

application specific integrated circuits,clocks,energy conservation,logic gates,optimisation,ASIC design cycle theory,EDA tools,clock gating,dynamic power,power optimization,power savings,ASIC,RTL,SoC,low power,optimization

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