Impact of porous SiOCH on propagation performance measured for narrow interconnects of the 45nm node

With the dimensions scaling down at each new technology node, introduction of porous dielectric materials is required to reduce the interconnect capacitance. Nevertheless, these materials are very prone to damage during integration, thus increasing their K-value (2.5 as deposited for the 45nm node) in the final circuit. In order to characterize these effects, high-frequency measurements and electromagnetic simulations were carried out on specific microstrip structures. Taking into account typical circuit characteristics, time-domain extraction of delay values and crosstalk levels were then performed, enabling a precise analysis of moisture uptake effects from a performance point of view.