FASER: fast analysis of soft error susceptibility for cell-based designs
San Jose, CA（2006）
摘要
This paper is concerned with statically analyzing the susceptibility of arbitrary combinational circuits to single event upsets that are becoming a significant concern for reliability of commercial electronics. For the first time, a fast and accurate methodology FASER based on static, vector-less analysis of error rates due to single event upsets in general combinational circuits is proposed. Accurate models are based on STA-like pre-characterization methods, and logical masking is computed via binary decision diagrams with circuit partitioning. Experimental results indicate that FASER achieves good accuracy compared to the SPICE-based simulation method. The average error across the benchmark circuits is 12% at over 90,000X speed-up. The accuracy can be further improved by more accurate cell library characterization. The run-time for ISCAS '85 benchmark circuits ranges from 10 to 120 minutes. The estimated bit error rate (BER) for the ISCAS'85 benchmark circuits implemented in the 100nm CMOS technology is about 10-5 FIT
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关键词
vector less analysis,spice,bit error rate,benchmark circuits,integrated circuit reliability,combinational circuits,binary decision diagrams,100 nm,benchmark circuits range,error analysis,circuit partitioning,error rate,commercial electronics reliability,accurate model,arbitrary combinational circuit,error rates,soft error susceptibility,fast analysis of soft error susceptibility,arbitrary combinational circuits,cmos technology,faser,accurate cell library characterization,static analysis,fast analysis,benchmark circuit,estimated bit error rate,single event upsets,accurate methodology,benchmark testing,spice-based simulation,cell-based designs,network analysis,average error,single event upset,logical masking,sleep mode,boolean functions,combinational circuit,data structures,circuit analysis,binary decision diagram,soft error,computational modeling
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