Efficient False Path Elimination Algorithms For Timing Verification By Event Graph Preprocessing
INTEGRATION-THE VLSI JOURNAL(1989)
摘要
Accurate timing verification and optimization methods require algorithms that exclude false paths. Recently published methods for critical path searches that eliminate false paths, can take long evaluation times for complex time-optimized circuits. In this paper a new
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关键词
Timing verification,false delay paths,path sensitization,graph algorithms
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