基本信息
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Bio
I am passionate about building high performance network systems by leveraging hardware/software co-design. I am currently working on the nanoPU, a novel CPU-NIC architecture designed to provide ultra low latency and high throughput. The nanoPU moves the entire network stack into line-rate hardware: programmable transport, core selection, and thread scheduling. It uses a novel register file network interface rather than the traditional DMA-based network interface in order to provide the lowest possible latency and most predictable performance. We developed an open source, end-to-end FPGA prototype that runs on AWS F1 instances using Firesim. The wire-to-wire latency through the nanoPU is just 69ns – an order of magnitude lower latency than state-of-the-art commercial NICs! The nanoPU also enables single-digit microsecond 99% tail latencies and message processing throughput of over 100 Mrps per-core. You can learn more about the nanoPU from our paper and this 30min talk.
Research Interests
Papers共 12 篇Author StatisticsCo-AuthorSimilar Experts
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CoRR (2022)
CoRR (2022)
Proceedings of the ACM SIGCOMM Symposium on SDN Research (SOSR) (2021)
Proceedings of the Workshop on Hot Topics in Operating Systems (2021)
CoRR (2020)
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