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个人简介
Sang H. Dhong (M'76–SM'99–F'01) received the B.S.E.E. degree from Korea University, Seoul, Korea, and the M.S. and Ph.D. degrees in electrical engineering from the University of California at Berkeley.
He joined IBM's Research Division in Yorktown Heights, NY, in 1983 as a research staff member, where he was involved in the research and development of silicon processing technology, mainly bipolar devices and reactive-ion etching (RIE). From 1985 to 1992, he was engaged in research and development of DRAM cell structures, architectures, and designs, spanning over five generations of IBM DRAMs, from 1 Mb DRAMs to 256 Mb DRAMs. The key contributions in this area are high-speed DRAMs, low-power DRAMs, and NMOS-access transistor trench DRAM cells. After spending three years in development of one of IBM's PowerPC microprocessors as a Branch/Icache circuit team leader of 15 designers, he worked on a simple but fast processor core based on the PowerPC architecture and on high-speed embedded DRAM (eDRAM) in the Austin Research Laboratory of the IBM Research Division, leading, managing, and growing the high-performance VLSI design group to a peak of 25 people from 1995 to 1999. The work resulted in setting a major milestone for the microprocessor industry by prototyping1-GHz PowerPC processors. Also, the work on the high-speed eDRAM provided the justification for the logic-based eDRAM foundry/ASIC technology offering by IBM as well as the design basis for eDRAM macros of DRAM-like density with SRAM-like high speed. Since becoming the Chief Technologist of the Austin Research Laboratory in 1999, he has worked in three areas: fast low-power embedded PowerPC, super-pipelined multi-gigahertz PowerPC servers, and high-speed eDRAM. In 2000, he joined the Sony-Toshiba-IBM (STI) Design Center as one of the key leaders, primarily concentrating on a 11-FO4 coprocessor design, streaming processing element (SPE). As the partition leader of SPE team, he defined, executed, and delivered the technology, circuits and latch styles, floor plan, and basic lower-power micro-architecture and led technically a multi-discipline team of 70 or more engineers. Currently, he is the chief hardware engineer/SPE partition lead, being responsible for productization of BE chip from the STI center side. In this role, his major focus is on power-frequency yield tradeoff, interacting and guiding PE, manufacturing, and design teams in a matrix organization of more than 100 engineers. He holds more than 125 U.S. patents and has many technical publications.
Dr. Dhong is an IBM Distinguished Engineer and a member of IBM Academy of Technology. He has received five Outstanding Innovation/Technical Achievement Awards from IBM.
研究兴趣
论文共 40 篇作者统计合作学者相似作者
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作者统计
#Papers: 40
#Citation: 1054
H-Index: 24
G-Index: 32
Sociability: 4
Diversity: 1
Activity: 0
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