基本信息
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Career Trajectory
Bio
Sanjay Parihar (Member, IEEE) received the B.Eng. degree in electrical engineering from McGill University, in 1987, and the Ph.D. degree in electrical engineering from Princeton University, in 1994. He joined the Advanced Products Research and Development Laboratory, Motorola, in 1995, where he carried out process integration of BiCMOS and CMOS nodes from 0.40
$\mu {\mathrm{ m}}$
to 90 nm. In 2002, he joined the Crolles 2 Alliance in France to work on 90 nm and 45 nm bulk CMOS Technologies. He returned to Freescale in 2006 and focused on sram memory specific challenges in 45 nm low power bulk technology and 45 nm high performance SOI Technology. In 2013, he joined GLOBALFOUNDRIES, Austin where he is currently a Member of the Technical Staff engaged in 12 nm node sram bitcell development. His research interests are sram bitcell design and margining.
Research Interests
Papers共 12 篇Author StatisticsCo-AuthorSimilar Experts
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Seong Yeol Mun,David Burnett,K. Y. Lim,Sanjay Parihar, Y. J. Shi,H. C. Lo,W. Hong,K. J. Lee,Owen Hu, J. Versaggi, C. Jerome,J. G. Lee,
2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)pp.1-2, (2017)
S. Narasimha,B. Jagannathan,A. Ogino,D. Jaeger,Brian J. Greene,C. Sheraw, K. Zhao, B. S. Haran,Unoh Kwon, A. K. M. Mahalingam,B. Kannan, B. Morganfeld,
2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)pp.1-3, (2016)
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