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Ram S. Viswanath (M’13) received the bachelor’s degree in mechanical engineering from the National Institute of Technology, Tiruchirappalli, India, and the master’s and Ph.D. degrees in mechanical and aerospace engineering from Rutgers University, New Brunswick, NJ, USA.
In 1993, he joined Intel Corporation, Chandler, AZ, USA, where he was involved in the 100-MHz Intel Pentium processor. Under his leadership, Intel’s Assembly and Test Technology Development organization has enabled technologies co-engineered with products to optimize for cost and performance at the front end. This involves co-optimizing silicon, I/O floor planning, and power-delivery and power-dissipation schemes to improve form factor and cost of packaging. Intel has recognized these efforts three times with Intel Achievement Awards, the highest recognition in Intel. He is currently the Vice President of the technology development organization and the Director of packaging architecture with Intel Corporation. He has authored or coauthored book chapters in the areas of package architecture, interconnects, and processor cooling. He has been granted multiple patents. He leads the team responsible for developing innovative packaging technologies for client, server, handheld, programmable, graphics, and communication processors.
Dr. Viswanath is a member of various research consortia, including an Executive Member of the International Electronics Manufacturing Initiative’s technical committee. He is also a respected expert outside Intel. He has delivered multiple keynote addresses at industry conferences and led panel discussions on interconnect scaling and heterogeneous integration.
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IEEE Transactions on Components, Packaging and Manufacturing Technologyno. 10 (2019): 1952-1962
IEEE Transactions on Components, Packaging and Manufacturing Technologypp.1-1, (2019)
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