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Nitanshu Chauhan (Member, IEEE) received the M.Tech. degree in VLSI from the Indian Institute of Technology Roorkee, Uttarakhand, India, in 2017, where he is currently pursuing the Ph.D. degree with the Department of Electronics and Communication Engineering. He is also associated with the Department of Electronics Engineering, NIT Uttarakhand, Srinagar. His current research interests include simulation, modeling of negative capacitance field-effect transistors, FeFET, and device circuit co-design.
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Amit Kumar,Shashank Banchhor, Pradyum Pal, Narendra Pratap, Shubham Kumar, Ashutosh Yadav,Sudeb Dasgupta,Anand Bulusu,Nitanshu Chauhan
2024 8th IEEE Electron Devices Technology & Manufacturing Conference (EDTM)pp.1-3, (2024)
Aditya Sharma, Vatsal Dixit,Dinesh Kushwaha,Nitanshu Chauhan, Vishal Kumar Saxena,Sudeb Dasgupta,Anand Bulusu
2024 25th International Symposium on Quality Electronic Design (ISQED)pp.1-8, (2024)
2023 7th IEEE Electron Devices Technology & Manufacturing Conference (EDTM)pp.1-3, (2023)
2023 IEEE INTERNATIONAL SYMPOSIUM ON APPLICATIONS OF FERROELECTRICS, ISAFpp.1-4, (2023)
IEEE International Reliability Physics Symposium (IRPS)pp.23-1, (2022)
2022 IEEE International Conference on Emerging Electronics (ICEE)pp.1-4, (2022)
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IEEE Open Journal of Ultrasonics, Ferroelectrics, and Frequency Control (2022): 55-64
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