Matt Becker

Matt Becker received the B.S., M.E., and Ph.D. degrees in electrical engineering from the Massachusetts Institute of Technology (MIT), Cambridge, MA, USA. He has 14 years' experience ranging across digital and analog circuit design, layout, logic architecture, signal integrity, timing, validation, etc. He joined Intel in 2001 leading a modulated IO SERDES project. Subsequently he was the chip lead for a receiver chip for the Electromagnetic Coupler Probe Project and the analog design lead for the High Performance Computing program. Most recently, he is the principal engineer responsible for the Xeon® DDR and FIVR IPs for Haswell Server and 10 nm. Prior to Intel, he worked at Sun Microsystems on the retiming execution unit for Ultrasparc 5 and in Sun Labs developing a series of four chips for the asynchronous circuit design project.