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个人简介
Liang-Teck Pang (S'02-M'08) received the Dipl.Ing. degree from Ecole Centrale de Paris, France, the M.Phil. degree from Cambridge University, U.K., in 1997, and the Ph.D. degree in the Department of Electrical Engineering and Computer Sciences at the University of California, Berkeley, in 2008. His Ph.D. research involved the design of circuits to measure and characterize CMOS performance variability due to fluctuations in the manufacturing process.
Between 1998 and 2002, he worked in the DSO National Labs in Singapore on VLSI implementation of signal processing algorithms and high performance microarchitecture and circuit design. In 2008, he joined IBM T. J. Watson Research Center, Yorktown Heights, NY, as a research staff member. His research emphasis is on the effects of layout on CMOS performance, measurement of the spatial correlation of logic gates, and analysis of variability data. Currently in IBM, his research focus is in clocking of high performance VLSI chips and 3-D chip design.
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