基本信息
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Career Trajectory
Bio
Ki-Tae Park received the B.S. degree in electronics engineering from Kyoungbook National University, South Korea, in 1993, and the M.S. and Ph.D. degrees in machine intelligence and system engineering from Tohoku University, Japan, in1993, and 1999, respectively.
From 1999 to 2001, he served as a Research Associate and involved in nanoCMOS devices, low power circuits, 3-D shared memories, and artificial retina chips with Tohoku University. From 2001 to 2004, he joined Halo LSI, NY, USA, in circuit design for high speed embedded flash and NAND compatible high density flash memories using SONOS technology. He joined Samsung Electronics Corporation, Hwasung, South Korea, in 2004, and has involved in design of MLC and TLC NAND flash memory products. He had been responsible for designing world’s first TLC NAND for SSD application. He also has been responsible for developing world’s first 3-D NAND product using vertical layer-stacking technology. He is currently a Vice-President with Samsung. He holds over 100 U.S. patents.
Dr. Park received several achievement awards from Samsung for his outstanding work.
Research Interests
Papers共 277 篇Author StatisticsCo-AuthorSimilar Experts
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International Journal of Highway Engineeringno. 1 (2023): 23-32
Journal of the Korean Society for Advanced Composite Structuresno. 6 (2022): 23-30
Hyeokjo Gwon,Kitae Park,Soon-Chun Chung,Ryoung-Hee Kim, Jin Kyu Kang,Sang Min Ji,Nag-Jong Kim, Sunghaeng Lee,Jun-Hwan Ku, Eun Cheol Do,Sujin Park,Minsang Kim,
2018 IEEE International Solid-State Circuits Conference - (ISSCC)pp.338-340, (2018)
Jaeyoung Choi,Aram Yang,Ari Song, Minji Lim,Jinsup Kim,Ja-Hyun Jang,Ki-Tae Park,SungYoon Cho,Dong-Kyu Jin
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