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个人简介
Katherine V. Hawkinsreceived a B.S. degree in materials science and engineering from the Massachusetts Institute of Technology in 1998 and a M.S. degree in materials science and engineering from NC State University in 2000. As a failure analysis engineer at IBM, she has worked on vertical cell DRAM technology, 90 nm SRAM arrays, and currently SRAM arrays on 45 nm SOI technology.
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论文共 5 篇作者统计合作学者相似作者
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International Symposium for Testing and Failure AnalysisISTFA 2013: Conference Proceedings from the 39th International Symposium for Testing and Failure Analysis (2013)
Nauman Z Butt,Kevin Mcstay,Alberto Cestero,Howard Ho,W Kong,S Fang,R S Krishnan,Babar A Khan, A Tessier, W Davies,S Lee, Yaping Zhang,
Electron Devices Meetingpp.27.5.1-27.5.4, (2010)
Xu Ouyang, David Riggs,Ishtiaq Ahsan,Oliver D Patterson, D Lea, Benjamin Ebersman,Katherine V Hawkins,Keith W Miller,S Fox, James Rice
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