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职业迁徙
个人简介
His research interests span various aspects of hardware design including VLSI design, computer architecture, FPGA, domain specific accelerators, hardware/software co-design, and agile hardware development. Before joining KAIST, Joo-Young was a Senior Hardware Engineering Lead at Microsoft Azure working on hardware acceleration for its hyper-scale big data analytics platform named Azure Data Lake. Before that, he was one of the initial members of Catapult project at Microsoft Research, where he deployed a fabric of FPGAs in
datacenters to accelerate critical cloud services such as machine learning, data storage, and networking.
Joo-Young is a recipient of the 2016 IEEE Micro Top Picks Award, the 2014 IEEE Micro Top Picks Award, the 2010 DAC/ISSCC Student Design Contest Award, the 2008 DAC/ISSCC Student Design Contest Award, and the 2006 A-SSCC Student Design Contest Award.
datacenters to accelerate critical cloud services such as machine learning, data storage, and networking.
Joo-Young is a recipient of the 2016 IEEE Micro Top Picks Award, the 2014 IEEE Micro Top Picks Award, the 2010 DAC/ISSCC Student Design Contest Award, the 2008 DAC/ISSCC Student Design Contest Award, and the 2006 A-SSCC Student Design Contest Award.
研究兴趣
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2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC)pp.533-538, (2024)
IEEE ACCESSno. 99 (2024): 11945-11962
IEEE Journal of Solid-State Circuitsno. 99 (2024): 1-13
IEEE JOURNAL OF SOLID-STATE CIRCUITS (2024)
CoRR (2024)
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IEEE Journal of Solid-State Circuitsno. 99 (2024): 1-12
IEEE J. Solid State Circuitsno. 3 (2024): 830-841
IEEE Solid-State Circuits Magazineno. 2 (2023): 151-154
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2023 IEEE Custom Integrated Circuits Conference (CICC)pp.1-2, (2023)
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