Jagdish Rao

Jagdish Rao has a B. E degree (1990), and has since been at Texas Instruments (India). Over the past 14 years, lagdish has worked on several high speed, low-cost DSP devices and ASICs, and successfully led the design methodology and physical implementation of several multi-million, nanometer SoC designs. Prior to this, he was also involved in co-architecting TI's first ASIC standard cell clock distribution system and joint development of standard cell place and route system with a major EDA company. lagdish has coauthored over 25 publications at various TI internal and external technical conferences and EDA forums. At TI, lagdish was elected Member Group Technical Staff in 1996 and Senior Member Technical Staff in 2000. He currently leads the Physical Design competency at TI's SoC Design Technology Center and also manages the DSP Physical Design group.