I-Min Liu

I-Min Liu received the B.S. and M.S. degrees in electronics engineering from the National Chiao Tung University, Hsinchu, Taiwan, R.O.C., in 1993 and 1995, respectively, and the Ph.D. degree in electrical and computer engineering from the University of Texas, Austin, in 2000. He joined the Silicon Perspective Corporation (SPC), Santa Clara, CA, in 2000, which merged into Cadence Design Systems, San Jose, CA, in 2002. Throughout his tenure with SPC, he was one of the main contributors in timing and signal integrity optimization for the virtual physical prototyping solution for 100+ million transistor designs. His work was later transformed into part of the foundation for Cadence's System-on-Chip optimization technology. With Cadence, he is currently focusing on the development of intelligent floorplanning and concurrent placement and optimization technologies. He is also involved with the methodology for multivoltage designs and with the hierarchical design methodology based on timing budgeting and interface logic modeling. His interest is in designing algorithms and providing solutions to solve complex design problems. Dr. Liu is a Member of Phi Tau Phi.