Po-Tsang Huang

Po-Tsang Huang (Member, IEEE) received the B.Sc., M.Sc., and Ph.D. degrees from the Department of Electronics Engineering, National Chiao Tung University (NCTU), Hsinchu, Taiwan, in 2002, 2004, and 2010, respectively. From 2011 to 2014, he was an Assistant Research Fellow with NCTU. From 2015 to 2017, he was an Associate Research Fellow with NCTU and a Visiting Scholar with the University of California at Los Angeles, Los Angeles, CA, USA. He is currently an Associate Professor with the International College of Semiconductor Technology, National Yang Ming Chiao Tung University (NYCU), Hsinchu. He has authored or coauthored more than 90 technical articles in renowned international journals and conferences and holds more than ten patents. His research interests include low-power digital IC design, embedded memory design, acceleration design for machine learning, low-power TSV 2.5-D/3-D integration, and low-power SoC/SiP designs with particular emphasis on interchip or intrachip data communications, and memory subsystems.