Caaliph Andriamisaina

Caaliph Andriamisaina received the M.Sc. degree in electronics and telecommunications technology from the Université de Bretagne Occidentale, Brest, France, in 2004, and the Ph.D. degree in computer science and electronic engineering from the Université de Bretagne Sud, Lorient, France, in 2008. From 2008 to 2010, he was a Post-Doctoral Researcher with the Lab-STICC, Université de Bretagne Sud, working on high-level synthesis algorithms. Since 2010, he joined CEA LIST Institute, Saclay, France, to work on the development of embedded multicore architectures. His current research interests include methodologies for power analysis optimization, co-emulation, and hardware accelerators.