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Bio
Have been actively working towards creating low-power high-speed I/O and energy-efficient 3D-stacked AI computing VLSI systems for more than 11 years. Collaborated with neuroscience researchers to invent the nonlinear neural network (NNN) which drastically reduces the number of neurons and synapses in neural networks. Also developed a wired-logic architecture-based NNN processor to realize orders-of-magnitude lower power and smaller chip implementation area. This innovation helps improve the energy efficiency of voice command recognition by three orders of magnitude by eliminating power-consuming DRAM access and implementing the entire neural network in one chip. Have published 25 journal papers and 39 peer-reviewed international conference papers. Serve as a TPC member for IEEE-sponsored conferences and guest editor for an IEEE journal.
Research Interests
Papers共 79 篇Author StatisticsCo-AuthorSimilar Experts
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IEEE Solid-State Circuits Letters (2024): 22-25
IEEE SOLID-STATE CIRCUITS LETTERS (2024): 22-25
2023 28th Asia and South Pacific Design Automation Conference (ASP-DAC)pp.182-183, (2023)
IEEE Solid-State Circuits Letters (2023): 65-68
Japanese Journal of Applied Physicsno. SC (2023): SC1019-SC1019
IEEE Journal of Solid-State Circuitsno. 7 (2023): 2075-2086
NEWCASpp.1-4, (2023)
2023 28th Asia and South Pacific Design Automation Conference (ASP-DAC)pp.180-181, (2023)
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