Ajey P. Jacob

Ajey P. Jacob (M'07) received the B. Sc. degree in physics from the University of Kerala, Kerala, India, in 1994, the M. Sc. degree in applied physics from Maharaja Sayajirao University of Baroda, Vadodara, Gujarat, India, in 1996, and the Ph.D. degree in physics from the Department of Nanoelectronics and Microtechnology (MC2), Chalmers University of Technology/Gothenburg University, Sweden, in 2002. In 2003, he cofounded the “Integrated Vertical Modules,” a start-up firm to develop 3-D integration of silicon chips for memory applications using ion-cut technology. He joined Intel Corporation in 2004, Santa Clara, CA as a Device Engineer, where he supported its high-volume manufacturing and research activities in various capacities, and is currently a Research Scientist at the Technology Strategy Department, Technology and Manufacturing Group and technically managing the “Western Institute of Nanoelectronics”—industry government consortia, and other strategic research projects. From 2004 to 2006, he was the Intel Technical Lead for several sub-32-nm nanotechnology-related EU research projects. He was an Industry Mentor in both U.S. and European Universities for several Ph.D. students and Postdoctoral Fellows. He has authored or coauthored more than 50 articles in refereed journals and conferences.