Alberto Cestero - Research & Technology Development, GLOBALFOUNDRIES

基本信息

Career Trajectory

Bio

Alberto Cestero received the B.S.E.E. and M.S.E.E. degrees in electronics from the University of Puerto Rico Mayaguez campus, Mayagüez, Puerto Rico, where his thesis included the development of a performance simulator of k-ary n cube parallel processor networks. He was a Board In-Circuit and a Functional Test Engineer with Storagetek, Ponce, Puerto Rico. He joined IBM, East Fishkill, NY, USA, in 2001. He is currently a Staff Product Test and a Characterization Engineer for GLOBALFOUNDRIES, East Fishkill. His current research interest includes test development and design verification of high-speed embedded DRAM, array device monitors, and eFUSE technology.

Research Interests

Papers共 28 篇Author StatisticsCo-AuthorSimilar Experts

By YearBy Citation主题筛选期刊级别筛选合作者筛选合作机构筛选

SRAM and Mixed-Signal Logic with Noise Immunity in 3nm Nano-Sheet Technology

R. Joshi,J. Frougier,A. Cestero, C. Castellanos, S. Chakraborty,C. Radens, M. Silvestre, S. Lucarini,I. Ahsan,E. Leobandung

IEEE Open Journal of the Solid-State Circuits Societyno. 99 (2025): 1-1

Cited0Views0EIWOSBibtex

High Performance Nanosheet Technology Optimized for 77 K

R. Bao, L. Qin,J. Frougier, S. Suk, M. Rabie, U. Bajpai, A. Chou, B. Nechay, M. Mohamed,R. Pujari, T. J Weir, K. Harmon, A. Varma, W. Armstrong-Moore,A. Cestero, S. Emans, P. Hundekar, R. Joshi, J. Li, X. Liu, S. Lucarini,C. Radens,S. Siddiqui, H. Trombley,A. Bryant, M. Hasanuzzaman, A. Majumdar, M. Sung,J. Zhang,E. Leobandung

2023 International Electron Devices Meeting (IEDM)（2023）

Cited2Views0EIWOSBibtex

Optical Performance and Reliability Assessment from Self-Aligned Single Mode Fiber Attach for O-band Silicon Photonics Platform

Jae Kyu Cho,Takako Hirokawa,John Pellerin,Benjamin Fasano,Yusheng Bian,Ken Giewont,Vaishnavi Karra, Koushik Ramachandra,Karen Nummy,Alberto Cestero, George Parker,Dave Riggs,Norman Robson,Ian Melville, Alexsander Janta-Polczynski, George Zhuo-Jie Wu,Daniel Berger,Richard Langlois,Thomas Houghton,Vikas Gupta

2022 IEEE 72nd Electronic Components and Technology Conference (ECTC) (2022)

Cited7Views0EIWOSBibtex

Early Design/Technology Exploration of BEOL Options for Hybrid Wafer Bonded Split-SRAM

Rahul Mathur,Mudit Bhargava,Heath Perry,Alberto Cestero,Frank Frederick,Daniel Smith,Daniel Fisher,Norman Robson,Brian Cline,Jaydeep P. Kulkarni

IEEE Transactions on Electron Devicesno. 12 (2022): 6731-6737

Cited0Views0EIWOSBibtex

3D-Split SRAM: Enabling Generational Gains in Advanced CMOS

R. Mathur,M. Bhargava, H. Perry,A. Cestero, F. Frederick, S. Hung, C. Chao,D. Smith, D. Fisher,N. Robson,X. Xu, P. Chandupatla, R. Balachandran,S. Sinha,B. Cline,J. P. Kulkarni

2021 IEEE Custom Integrated Circuits Conference (CICC)（2021）

Cited4Views0EIWOSBibtex

A High-Density Logic-on-logic 3DIC Design Using Face-to-face Hybrid Wafer-Bonding on 12nm FinFET Process

S. Sinha, S. Hung, D. Fisher,X. Xu, C. Chao, P. Chandupatla, F. Frederick, H. Perry,D. Smith,A. Cestero,J. Safran, V Ayyavu,M. Bhargava,R. Mathur,D. Prasad, R. Katz, A. Kinsbruner,J. Garant,J. Lubguban,S. Knickerbocker, V Soler,B. Cline,R. Christy, T. McLaurin,N. Robson,D. Berger

2020 IEEE International Electron Devices Meeting (IEDM)（2020）

Cited14Views0EIWOSBibtex

80-Kb Logic Embedded High-K Charge Trap Transistor-Based Multi-Time-Programmable Memory with No Added Process Complexity

Balaji Jayaraman,Derek Leu,Janakiraman Viraraghavan,Alberto Cestero,Ming Yin,John Golz,Rajesh Reddy Tummuru,Ramesh Raghavan,Dan Moy,Thejas Kempanna,Faraz Khan,Toshiaki Kirihata,Subramanian S. Iyer

IEEE Journal of Solid-State Circuits（2018）

Cited19Views0EIWOSBibtex

14-Nm FinFET 1.5 Mb Embedded High-K Charge Trap Transistor One Time Programmable Memory Using Differential Current Sensing

Eric Hunt-Schroeder,Darren Anand,John Fifield,Michael Roberge,Dale Pontius,Mark Jacunski,Kevin Batson, Matthew Deming,Faraz Khan,Dan Moy,Alberto Cestero,Robert Katz,Zakariae Chbili,Edmund Banghart,Liu Jiang,Balaji Jayaraman,Rajesh R. Tummuru,Ramesh Raghavan, Amit Mishra,Norman Robson,Toshiaki Kirihata

IEEE Solid-State Circuits Lettersno. 12 (2018): 233-236

Cited5Views0EIWOSBibtex

MTPM Ramped Programming Optimization Methodology

Y. Mamy Randriamihaja,W. McMahon,A. Kerber,Z. Chbili,B. Parameshwaran,T. Kirihata,A. Cestero,N. Robson,D. Moy, R. Katz,D. Anand, J. Pape,S. S. Iyer

2017 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS)（2017）

Cited0Views0EIWOSBibtex

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