基本信息
浏览量:28
职业迁徙
个人简介
Current: Memory System, Interconnect, Coherence Protocol, and general System Architect for next-generation design at AMD.
Previous:
2012-2014: Samsung Austin Research Center (SARC): Principal System Performance Architect for clean-sheet ARM ISA custom on-chip interconnect, DRAM controller, and CPU last level cache for IP designs targeting multiple market segments. Management and oversight for a small (5-8) team of performance analysts and modeling engineers. Work with RTL /Design teams on definition (considering performance, functional correctness, etc) of above items including Mobile Memory System QoS. Sidelines in core uArch and Power Management algorithms, modeling, and design for Mobile.
2009-2012: System Architect for future AMD Opteron-family processor and future platform. Primary technical liason between program Chief Engineer and technical teams spanning SOC, microarchitecture, platform architecture, performance evaluation, etc disciplines exploring multiple technical aspects and coordination of design.
2003-2009: Computer architecture/system performance modeling and architecture. Special emphasis on multiprocessors (CMP, SMP) and memory systems (last level cache, DRAM, coherent interconnect/coherence protocols, etc.)
Additional experience in processor core microarchitecture and performance, including various aspects of power management.
Goals: Improve computer system performance through high performance design of above.
Specialties: Server architecture, memory system design/performance.
研究兴趣
论文共 1 篇作者统计合作学者相似作者
按年份排序按引用量排序主题筛选期刊级别筛选合作者筛选合作机构筛选
时间
引用量
主题
期刊级别
合作者
合作机构
作者统计
合作学者
合作机构
D-Core
- 合作者
- 学生
- 导师
数据免责声明
页面数据均来自互联网公开来源、合作出版商和通过AI技术自动分析结果,我们不对页面数据的有效性、准确性、正确性、可靠性、完整性和及时性做出任何承诺和保证。若有疑问,可以通过电子邮件方式联系我们:report@aminer.cn